The present invention relates to a television composite video signal processing circuit used for reading out a composite video signal from a disk memory in a still video floppy system to display the readout composite video signal on a television monitor.
Conventional television systems employ a 1/2 interlaced scanning procedure. For example, in the NTSC system, a vertical scanning period of one field is 262.5H (where H is the period of the horizontal sync signal). One frame consists of two fields which include 525 horizontal scanning lines. For this reason, when one-field composite video signal is repeatedly reproduced from the disk memory of the still video floppy system which stores the one-field composite video signal, i.e., a 262.5H composite video signal in one track of the disk memory, the horizontal sync signal is deviated by 0.5H at the start point or the end point of each track. In a normal television receiver, distortion occurs on the screen due to this deviation, and a normal display cannot be performed. Demand has arisen for causing a 0.5H delay circuit to delay the signal reproduced from the disk memory for every other field and producing signals so as to generate horizontal sync pulses at substantially equal time intervals throughout a plurality of fields.
When the 0.5H delay circuit is constituted by a charge-coupled device, a level of the reproduction signal is changed by nonlinear signal attenuation. A level difference between the composite video signal which is delayed for every other field and the nondelayed composite video signal occurs, thus changing the brightness on a television monitor at the frame frequency. As a result, the screen image flickers, deteriorating the quality of the screen image. In particular, when the peak level of the video signal is high and the screen image is bright, intense flickering is observed. Even if the peak level of the video signal is changed by about 1%, annoying flickering which is sensible to eyes occurs.